The present invention relates to a memory system, and more particularly to one making use of defective memory chips. After being manufactured, it is not unusual to find a memory chip, e.g. a DRAM chip, to be defective only in the logically upper (or lower) half thereof. As an example, a DRAM chip made by TI has a logical upper and a logical lower halves, each of which is accessible depending on the value of specific address bit at the negative-going edge of row address strobe (RAS) signal. It will be of a great saving if all of half defective memory chips are used in a computer memory system instead of being discarded.
It has been known in a most conventional system to utilize the defective memory chips in a mutually complementary manner which means combining a chip defective only in its upper half with another chip defective only in its lower half can logically constitute a perfect memory chip. If the chip manufacturer, however, finds out the defective chips are defective, for the most cases, in their upper (or lower) halves, the above-mentioned mutually complementary arrangement will be no more applicable.